HD6417751 Datasheet, PDF (859/1105 Pages) Renesas Technology Corp – SuperH RISC engine

22.2.4 PCI Configuration Register 3 (PCICONF3)
Bit:
Initial value:
PCI-R/W:
PP Bus-R/W:
31
BIST7
0
R
R
30
BIST6
0
R
R
29
BIST5
0
R
R
28
BIST4
0
R
R
27
BIST3
0
R
R
26
BIST2
0
R
R
25
BIST1
0
R
R
24
BIST0
0
R
R
Bit:
Initial value:
PCI-R/W:
PP Bus-R/W:
23
HEAD7
0
R
R
22
HEAD6
0
R
R
21
HEAD5
0
R
R
20
HEAD4
0
R
R
19
HEAD3
0
R
R
18
HEAD2
0
R
R
17
HEAD1
0
R
R
16
HEAD0
0
R
R
Bit:
Initial value:
PCI-R/W:
PP Bus-R/W:
15
LAT7
0
R/W
R/W
14
LAT6
0
R/W
R/W
13
LAT5
0
R/W
R/W
12
LAT4
0
R/W
R/W
11
LAT3
0
R/W
R/W
10
LAT2
0
R/W
R/W
9
LAT1
0
R/W
R/W
8
LAT0
0
R/W
R/W
Bit: 7
6
5
4
3
2
1
0
CACHE7 CACHE6 CACHE5 CACHE4 CACHE3 CACHE2 CACHE1 CACHE0
Initial value: 0
0
0
0
0
0
0
0
PCI-R/W: R
R
R
R
R
R
R
R
PP Bus-R/W: R
R
R
R
R
R
R
R
The PCI configuration register 3 (PCICONF3) is a 32-bit read/partial-write register that includes
the BIST function, header type, latency timer, and cache line size PCI configuration registers
stipulated in the PCI local bus specification. The BIST function is read from bits 31 to 24, the
header type from bits 23 to 16, the cache line size from bits 7 to 0. The guaranteed time for the
PCIC to occupy the PCI bus when the PCIC is master is set in bits 15-8 (latency timer).
Bits 15 to 8 can be written to. Other bits are fixed in hardware.
The PCICONF3 register is initialized to H'00000000 at a power-on reset and software reset.
Rev. 3.0, 04/02, page 819 of 1064