HD6417751 Datasheet, PDF (525/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Start
Initial settings
(SAR, DAR, DMATCR,
CHCR, DMAOR)
DE, DME = 1?
No
Yes
Illegal address check ^*4
(reflected in AE bit)
No
NMIF, AE, TE = 0?
Yes
Transfer
No
request issued?
*1
Yes
Transfer (1 transfer unit)
DMATCR - 1 → DMATCR
Update SAR, DAR
No
DMATCR = 0?
Yes
DMTE interrupt request
(when IE = 1)
*2
Bus mode,
*3
transfer request mode,
detection
method
NMIF or
No
AE = 1 or DE = 0 or
DME = 0?
Yes
Transfer suspended
NMIF or
AE = 1 or DE = 0 or
DME = 0?
Yes
End of transfer
No
Normal end
Notes: *1 In auto-request mode, transfer begins when the NMIF, AE, and TE bits are all 0, and the DE
and DME bits are set to 1.
*2
level detection (external request) in burst mode, or cycle steal mode
*3
edge detection (external request) in burst mode, or auto-request mode in burst mode
*4 An illegal address is detected by comparing bits TS2–TS0 in CHCRn with SARn and DARn
Figure 14.2 DMAC Transfer Flowchart
Rev. 3.0, 04/02, page 485 of 1064