HD6417751 Datasheet, PDF (491/1105 Pages) Renesas Technology Corp – SuperH RISC engine

13.3.9 Byte Control SRAM Interface
The byte control SRAM interface is a memory interface that outputs a byte select strobe (:(Q) in
both read and write bus cycles. It has 16 bit data pins, and can be connected to SRAM which has
an upper byte select strobe and lower byte select strobe function such as UB and LB.
Areas 1 and 4 can be designated as byte control SRAM interface. However, when these areas are
set to MPX mode, MPX mode has priority.
The byte control SRAM interface write timing is the same as for the normal SRAM interface.
In read operations, the :(Q pin timing is different. In a read access, only the :( signal for the
byte being read is asserted. Assertion is synchronized with the fall of the CKIO clock, as for the
:( signal, while negation is synchronized with the rise of the CKIO clock, using the same timing
as the 5' signal.
32-byte transfer is performed consecutively for a total of 32 bytes according to the set bus width.
The first access is performed on the data for which there was an access request. The remaining
accesses are performed in wrap-around fashion on the data at the 32-byte boundary. The bus is not
released during this period.
Figure 13.68 shows an example of byte control SRAM connection to the SH7751 Series, and
figures 13.69 to 13.71 show examples of byte control SRAM read cycles.
SH7751 Series
A18–A3
CSn
RD
RD/WR
D31–D16
WE3
WE2
D15–D0
WE1
WE0
64k × 16-bit
SRAM
A15–A0
CS
OE
WE
I/O15–I/O0
UB
LB
A15–A0
CS
OE
WE
I/O15–I/O0
UB
LB
Figure 13.68 Example of 52-Bit Data Width Byte Control SRAM
Rev. 3.0, 04/02, page 451 of 1064