HD6417751 Datasheet, PDF (30/1105 Pages) Renesas Technology Corp – SuperH RISC engine

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Sample Initialization Flowchart .................................................................... 695
Sample Transmission Processing Flowchart.................................................. 697
Sample Reception Processing Flowchart....................................................... 699
Receive Data Sampling Timing in Smart Card Mode .................................... 701
Retransfer Operation in SCI Receive Mode................................................... 702
Retransfer Operation in SCI Transmit Mode ................................................. 703
Procedure for Stopping and Restarting the Clock .......................................... 704
16-Bit Port A ............................................................................................... 708
16-Bit Port B................................................................................................ 709
SCK Pin....................................................................................................... 710
TxD Pin ....................................................................................................... 711
RxD Pin....................................................................................................... 711
MD1/TxD2 Pin ............................................................................................ 712
MD2/RxD2 Pin ............................................................................................ 712
MD0/SCK2 Pin............................................................................................ 713
MD7/CTS2 Pin ............................................................................................ 714
MD8/RTS2 Pin ............................................................................................ 715
Block Diagram of INTC ............................................................................... 730
Example of IRL Interrupt Connection........................................................... 733
Interrupt Operation Flowchart ...................................................................... 748
Block Diagram of User Break Controller ...................................................... 752
User Break Debug Support Function Flowchart ............................................ 772
Block Diagram of H-UDI Circuit.................................................................. 778
TAP Control State Transition Diagram ......................................................... 798
H-UDI Reset ................................................................................................ 799
PCIC Block Diagram ................................................................................... 803
PIO Memory Space Access .......................................................................... 887
PIO I/O Space Access .................................................................................. 888
Local Address Space Accessing Method....................................................... 889
Example of DMA Transfer Control Register Settings.................................... 893
Example of DMA Transfer Flowchart........................................................... 895
Master Write Cycle in Host Mode (Single) ................................................... 899
Master Read Cycle in Host Mode (Single) .................................................... 900
Master Memory Write Cycle in Non-Host Mode (Burst) ............................... 901
Master Memory Read Cycle in Non-Host Mode (Burst)................................ 902
Target Read Cycle in Non-Host Mode (Single) ............................................. 904
Target Write Cycle in Non-Host Mode (Single) ............................................ 905
Target Memory Read Cycle in Host Mode (Burst) ........................................ 906
Target Memory Write Cycle in Host Mode (Burst) ....................................... 907
Master Memory Write Cycle in Host Mode (Burst, With Stepping)............... 908
Target Memory Read Cycle in Host Mode (Burst, With Stepping) ................ 909
Endian Conversion Modes for Peripheral Bus ............................................... 910
Peripheral Bus ↔ PCI Bus Data Alignment .................................................. 911
Rev. 3.0, 04/02, page xxviii of xxxviii