HD6417751 Datasheet, PDF (963/1105 Pages) Renesas Technology Corp – SuperH RISC engine

When using this mode, note the CKIO load capacitance and only use it within the prescribed load
stated in the manual. Note, too, that the clock frequency of CKIO cannot be guaranteed until the
PLL oscillation stabilizes after a power-on reset or the clock frequency is changed. Also, in
standby mode, the clock stops. This mode should only be employed after checking that these
points do not cause any problems from the viewpoint of the system configuration.
In CKIO operating mode, the maximum Bφ frequency is 66 MHz.
When not using the PCICLK pin, fix the pin level high.
66 MHz Compatibility: The PCIC is not necessarily fully compatible with the 66 MHz bus
standard of the PCI. For details, see section 23, Electrical Characteristics. In the electrical
characteristics of the PCI bus-related pins, the permissible delay on the board is extremely short.
For this reason, the on-board load capacitance and impedance matching should be considered
before connecting to a 66MHz-compatible PCI device. Note, too, that only one PCI device can be
connected.
In the PCI standard, there are two methods for checking if a PCI device can operate at 66 MHz:
checking the 66 MHz operating status in the configuration register 1, and monitoring the 0(1%
pin in the PCI bus standard. The PCIC supports the 66 MHz operating status (66M) bit of the
configuration register 1 (PCICONF1). The PCIC does not have a special pin for directly
monitoring the 0(1% pin. Also, there is no control output pin for switching between 33 MHz
and 66 MHz when an external oscillator is used. A special external circuit is required to effect
these controls.
22.9 Power Management
22.9.1 Power Management Overview
The PCIC supports the PCI power management (version 1.0 compatible) configuration registers.
These are as follows:
• Support for the PCI power management control configuration register;
• Support for the power-down/restore request interrupts from hosts on the PCI bus.
There are three configuration registers for PCI power management control. PCI configuration
register 13 shows the address offset (CAPPTR) of the configuration registers for power
management. In the PCIC, this offset is fixed at CAPPTR = H'40. PCI configuration register 16
and PCI configuration register 17 are power management registers. They support two states:
power state D0 (normal) and power state D3 (power down mode).
The PCIC detects when the power state (PWRST) bit of the PCI configuration register 17 changes
(when it is written to from an external PCI device), and issues a power management interrupt. To
control the power management interrupts, there are a PCI power management interrupt register
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