HD6417751 Datasheet, PDF (368/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bit: 15
14
13
12
11
10
9
8
Bit name: MEMMODE A1MPX A4MPX —
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
Bit name: —
—
—
—
—
—
— SDBL
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R/W
Bit 15A1MPX/A4MPX Enable (MEMMODE): Determines whether or not the selection of
either the MPX interface or the SRAM interface is by A1MPX and A4MPX rather than by
MEMMPX.
Bit 15: MEMMODE
0
1
Description
MPX or SRAM interface is selected by MEMMPX
(Initial value)
MPX or SRAM interface is selected by A1MPX and A4MPX
Bits 14, 13MPX-Interface Specification for Area 1 and 4 (A1MPX, A4MPX): These bits
specify the types of memory connected to areas 1 and 4. These settings are validated by
MEMMODE.
Bit 14: A1MPX
0
1
Description
SRAM/byte control SRAM interface is selected for area 1
MPX interface is selected for area 1
(Initial value)
Bit 13: A4MPX
0
1
Description
SRAM/byte control SRAM interface is selected for area 4
MPX interface is selected for area 4
(Initial value)
Bit 0Burst Length (SDBL): Sets the burst length when the synchronous DRAM interface is
used. The burst-length setting is only valid when the bus width is 32 bits.
Bit 0: SDBL
0
1
Description
Burst length is 8
Burst length is 4
(Initial value)
Rev. 3.0, 04/02, page 328 of 1064