HD6417751 Datasheet, PDF (888/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bit 1—Master Write !## Detection Interrupt (M_DPERR_WT): When the PCIC is master.
3(55 received from the target while writing data to the target. Detects only when bit 6 (PER) of
the PCICONF1 is 1.
Bit 0—Master Read Data Parity Error Interrupt (M_DPERR_RD): When the PCIC is master,
a parity error was detected during a data read from the target. Detects only when bit 6 (PER) of the
PCICONF1 is 1.
22.2.21 PCI Interrupt Mask Register (PCIINTM)
Bit: 31
30
29
28
27
26
25
24
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
PCI-R/W: R
R
R
R
R
R
R
R
PP Bus-R/W: R
R
R
R
R
R
R
R
Bit: 23
22
21
20
19
18
17
16
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
PCI-R/W: R
R
R
R
R
R
R
R
PP Bus-R/W: R
R
R
R
R
R
R
R
Bit: 15
14
13
12
11
10
9
8
M_LOCK T_TGT_A —
—
—
— TGT_RET MST_DIS
ON BORT
RY
Initial value: 0
0
0
0
0
0
0
0
PCI-R/W: R/W
R/W
R
R
R
R
R/W
R/W
PP Bus-R/W: R/W
R/W
R
R
R
R
R/W
R/W
Bit: 7
6
5
4
3
2
1
0
ADRPER SERR_D T_DPER T_PERR_ M_TGT_AM_MST_ M_DPER M_DPER
R
ET R_WT DET BORT ABORT R_WT R_RD
Initial value: 0
0
0
0
0
0
0
0
PCI-R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PP Bus-R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The PCI interrupt mask register (PCIINTM) sets the respective interrupt masks for the interrupts
generated when errors occur in PCI transfers. It is a 32-bit read/write register that can be accessed
Rev. 3.0, 04/02, page 848 of 1064