HD6417751 Datasheet, PDF (333/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bit 0—Counter Start 3 (STR3): Specifies whether timer counter 3 (TCNT3) is operated or
stopped.
Bit 0: STR3
0
1
Description
TCNT3 count operation is stopped
TCNT3 performs count operation
(Initial value)
12.2.4 Timer Constant Registers (TCOR)
The TCOR registers are 32-bit readable/writable registers. There are five TCOR registers, one for
each channel.
When a TCNT counter underflows while counting down, the TCOR value is set in that TCNT,
which continues counting down from the set value.
The TCOR registers in channels 0 to 2 are initialized to H'FFFFFFFF by a power-on or manual
reset, but are not initialized and retain their contents in standby mode.
The TCOR registers in channels 3 and 4 are initialized to H'FFFFFFFF by a power-on reset, but
are not initialized and retain their contents by a manual reset or in standby mode.
Bit: 31
30
29
2
1
0
·············
Initial value: 1
1
1
1
1
1
R/W: R/W
R/W
R/W
R/W
R/W
R/W
12.2.5 Timer Counters (TCNT)
The TCNT registers are 32-bit readable/writable registers. There are five TCNT registers, one for
each channel.
Each TCNT counts down on the input clock selected by TPSC2–TPSC0 in the timer control
register (TCR).
When a TCNT counter underflows while counting down, the underflow flag (UNF) is set in the
corresponding timer control register (TCR). At the same time, the timer constant register (TCOR)
value is set in TCNT, and the count-down operation continues from the set value.
The TCNT registers in channels 0 to 2 are initialized to H'FFFFFFFF by a power-on or manual
reset, but are not initialized and retain their contents in standby mode.
Rev. 3.0, 04/02, page 293 of 1064