HD6417751 Datasheet, PDF (396/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bit 2—Refresh Count Overflow Flag (OVF): Status flag that indicates that the number of
refresh requests indicated by the refresh count register (RFCR) has exceeded the number specified
by the LMTS bit in RTCSR.
Bit 2: OVF
Description
0
RFCR has not overflowed the count limit indicated by LMTS
[Clearing condition]
When 0 is written to OVF
1
RFCR has overflowed the count limit indicated by LMTS
[Setting condition]
When RFCR overflows the count limit set by LMTS*
Note: * If 1 is written, the original value is retained.
(Initial value)
Bit 1—Refresh Count Overflow Interrupt Enable (OVIE): Controls generation or suppression
of an interrupt request when the OVF flag is set to 1 in RTCSR.
Bit 1: OVIE
0
1
Description
Interrupt requests initiated by OVF are disabled
Interrupt requests initiated by OVF are enabled
(Initial value)
Bit 0—Refresh Count Overflow Limit Select (LMTS): Specifies the count limit to be compared
with the refresh count indicated by the refresh count register (RFCR). If the RFCR register value
exceeds the value specified by LMTS, the OVF flag is set.
Bit 0: LMTS
0
1
Description
Count limit is 1024
Count limit is 512
(Initial value)
13.2.12 Refresh Timer Counter (RTCNT)
The refresh timer counter (RTCNT) is an 8-bit readable/writable counter that is incremented by
the input clock (selected by bits CKS2–CKS0 in the RTCSR register). When the RTCNT counter
value matches the RTCOR register value, the CMF bit is set in the RTCSR register and the
RTCNT counter is cleared.
RTCNT is initialized to H'0000 by a power-on reset, but continues to count when a manual reset is
performed. In standby mode, RTCNT is not initialized, and retains its contents.
Rev. 3.0, 04/02, page 356 of 1064