HD6417751 Datasheet, PDF (157/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Example 3: When an instruction at which an exception occurs is a branch instruction but a branch is not made
Instruction 1 (branch instruction) ; Address of this instruction is saved to SPC when exception occurs.
Instruction 2 ; May be executed if an SQ store instruction.
Instruction 3 ; May be executed if an SQ store instruction.
Instruction 4 ; May be executed if an SQ store instruction.
Instruction 5
Both A and B below must be satisfied in order to prevent this bug.
A: When a store queue store instruction is executed after a PREF instruction for transfer from that
same store queue (SQ0, SQ1) to external memory, (1) and (2) below must be satisfied.
(1) Insert three NOP instructions*¹ between the two instructions.
(2) Do not place a PREF instruction for transfer from a store queue to external memory in the
delay slot of a branch instruction.
B: Do not execute a PREF instruction for transfer from a store queue to external memory within
an exception handling routine.
If the above is executed and there is a store queue store instruction among the four
instructions*² including the instruction at the address indicated by the SPC, the state of the
contents transferred to external memory by the PREF instruction may be that when execution
of this store instruction is completed.
Notes: *1 If there are other instructions between the two instructions, this bug can be prevented if
the total number of other instructions plus NOP instructions is at least three.
*2 If the instruction at the address indicated by the SPC is a branch instruction, this also
applies to two instructions at the branch destination.
Rev. 3.0, 04/02, page 117 of 1064