HD6417751 Datasheet, PDF (11/1105 Pages) Renesas Technology Corp – SuperH RISC engine

9.5.1 Transition to Pin Sleep Mode........................................................................... 225
9.5.2 Exit from Pin Sleep Mode................................................................................ 225
9.6 Standby Mode.............................................................................................................. 225
9.6.1 Transition to Standby Mode............................................................................. 225
9.6.2 Exit from Standby Mode.................................................................................. 226
9.6.3 Clock Pause Function ...................................................................................... 227
9.7 Module Standby Function ............................................................................................ 227
9.7.1 Transition to Module Standby Function ........................................................... 227
9.7.2 Exit from Module Standby Function ................................................................ 228
9.8 Hardware Standby Mode.............................................................................................. 229
9.8.1 Transition to Hardware Standby Mode ............................................................. 229
9.8.2 Exit from Hardware Standby Mode.................................................................. 229
9.8.3 Usage Notes .................................................................................................... 230
9.9 STATUS Pin Change Timing ....................................................................................... 230
9.9.1 In Reset ........................................................................................................... 230
9.9.2 In Exit from Standby Mode.............................................................................. 231
9.9.3 In Exit from Sleep Mode.................................................................................. 233
9.9.4 In Exit from Deep Sleep Mode......................................................................... 236
9.9.5 Hardware Standby Mode Timing ..................................................................... 238
Section 10 Clock Oscillation Circuits ........................................................................ 241
10.1 Overview ..................................................................................................................... 241
10.1.1 Features........................................................................................................... 241
10.2 Overview of CPG......................................................................................................... 243
10.2.1 Block Diagram of CPG.................................................................................... 243
10.2.2 CPG Pin Configuration.................................................................................... 246
10.2.3 CPG Register Configuration ............................................................................ 246
10.3 Clock Operating Modes................................................................................................ 247
10.4 CPG Register Description ............................................................................................ 249
10.4.1 Frequency Control Register (FRQCR) ............................................................. 249
10.5 Changing the Frequency............................................................................................... 251
10.5.1 Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 is Off)........... 251
10.5.2 Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 is On)............ 251
10.5.3 Changing Bus Clock Division Ratio (When PLL Circuit 2 is On) ..................... 252
10.5.4 Changing Bus Clock Division Ratio (When PLL Circuit 2 is Off)..................... 252
10.5.5 Changing CPU or Peripheral Module Clock Division Ratio.............................. 252
10.6 Output Clock Control ................................................................................................... 253
10.7 Overview of Watchdog Timer ...................................................................................... 253
10.7.1 Block Diagram ................................................................................................ 253
10.7.2 Register Configuration..................................................................................... 254
10.8 WDT Register Descriptions.......................................................................................... 254
10.8.1 Watchdog Timer Counter (WTCNT)................................................................ 254
10.8.2 Watchdog Timer Control/Status Register (WTCSR)......................................... 255
Rev. 3.0, 04/02, page ix of xxxviii