HD6417751 Datasheet, PDF (935/1105 Pages) Renesas Technology Corp – SuperH RISC engine

DMA transfer start
DMA transfer starts when 1 is set in the DMASTRT
bit of the PCIDCR register.
DMA transfer (⇔ FIFO)
Transfer address update
The PCIDPA and PCIDLA registers are updated
(increment/fixed) by the LAHOLD bit of the
PCIDCR register.
Transfer count decrement
The PCIDTC decrements at a rate equaling the
number of transfer bytes (4 bytes).
Is transfer
Yes
error detected?
No
DMASTOP = 1?
Yes
No
Yes
PCIDTC > 0?
No
DMAST = 0
DMA transfer is forcibly
stopped when 1 is set in the
DMASTOP bit of the PCIDCR
register. (Do not set 1 in the
DMASTRT bit at the same
time.)
DMAST = 1
Normal ending
Abnormal ending
After DMA transfer completion, the DMASTRT bit of the PCIDCR register is
cleared to 0, and the DMAIS bit of the PCIDCR register is set to 1.
Figure 22.6 Example of DMA Transfer Flowchart
• Termination by software reset
When the RSTCTL bit of the PCICR is asserted, the PCIC is reset and DMA transfers are
forcibly terminated. Note, however, that when transfers are terminated by a software reset, the
PCIDCR is also reset and the DMA transfer control registers are all cleared.
Rev. 3.0, 04/02, page 895 of 1064