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HD6417751 Datasheet, PDF (256/1105 Pages) Renesas Technology Corp – SuperH RISC engine | |||
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Table 9.1 Status of CPU and Peripheral Modules in Power-Down Modes
Status
Power-
Down Entering
Mode Conditions CPG
CPU
On-chip
On-Chip Peripheral
Memory Modules Pins
Sleep
SLEEP Operating Halted Held
instruction
(registers
executed
held)
while STBY
bit is 0 in
STBCR
Operating Held
Deep
sleep
SLEEP Operating Halted Held
instruction
(registers
executed
held)
while STBY
bit is 0 in
STBCR,
and DSLP
bit is 1 in
STBCR2
Operating Held
(DMA
halted)
Standby SLEEP Halted
instruction
executed
while STBY
bit is 1 in
STBCR
Halted Held
(registers
held)
Halted* Held
Hard- Setting CA Halted
ware pin to low
standby level
Halted
Unde- Halted*
fined
High-
imped-
ance
state
Module Setting Operating Operating Held
standby MSTP bit to
1 in STBCR
Specified
modules
halted*
Held
External Exiting
Memory Method
Refresh- ⢠Interrupt
ing
⢠Reset
Self- ⢠Interrupt
refresh-
ing
⢠Reset
Self- ⢠Interrupt
refresh-
ing
⢠Reset
Unde- ⢠Power-on
fined
reset
Refresh- ⢠Clearing
ing
MSTP bit
to 0
⢠Reset
Note: * The RTC operates when the START bit in RCR2 is 1 (see section 11, Realtime Clock
(RTC)).
Rev. 3.0, 04/02, page 216 of 1064
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