HD6417751 Datasheet, PDF (348/1105 Pages) Renesas Technology Corp – SuperH RISC engine

13.1.3 Pin Configuration
Table 13.1 shows the BSC pin configuration.
Table 13.1 BSC Pins
Name
Signals
I/O
Address bus
A25–A0
O
Data bus
D31–D0
I/O
Bus cycle start %6
O
Chip select 6–0 &6–&6
O
Read/write
RD/:5
O
Row address
5$6
O
strobe
Read/column
5'/&$66/
O
address strobe/ )5$0(
cycle frame
Data enable 0 :(/5(*
O
Data enable 1
:(
O
Data enable 2 :(/,&,25' O
Data enable 3 :(/,&,2:5 O
Description
Address output
Data input/output
Signal that indicates the start of a bus cycle
When setting synchronous DRAM interface or MPX
interface: asserted once for a burst transfer
For other burst transfers: asserted each data cycle
Chip select signals that indicate the area being
accessed
&6 and &6 are also used as PCMCIA &($ and
&(%
Data bus input/output direction designation signal
Also used as the DRAM/synchronous
DRAM/PCMCIA interface write designation signal
5$6 signal when setting DRAM/synchronous DRAM
interface
Strobe signal that indicates a read cycle
When setting synchronous DRAM interface: &$6
signal
When setting MPX interface: )5$0( signal
When setting PCMCIA interface: 5(* signal
When setting SRAM interface: write strobe signal for
D7–D0
When setting PCMCIA interface: write strobe signal
When setting SRAM interface: write strobe signal for
D15–D8
When setting PCMCIA interface: ,&,25' signal
When setting SRAM interface: write strobe signal for
D23–D16
When setting PCMCIA interface: ,&,2:5 signal
When setting SRAM interface: write strobe signal for
D31–D24
Rev. 3.0, 04/02, page 308 of 1064