HD6417751 Datasheet, PDF (371/1105 Pages) Renesas Technology Corp – SuperH RISC engine

13.2.5 Wait Control Register 1 (WCR1)
Wait control register 1 (WCR1) is a 32-bit readable/writable register that specifies the number of
idle state insertion cycles for each area. With some kinds of memory, data bus drive does not go
off immediately after the read signal from off-chip goes off. As a result, there is a possibility of a
data bus collision when consecutive memory accesses are performed on memory in different
areas, or when a memory write is performed immediately after a read. In the SH7751 Series, the
number of idle cycles set in the WCR1 register are inserted automatically if there is a possibility of
this kind of data bus collision.
WCR1 is initialized to H'77777777 by a power-on reset, but is not initialized by a manual reset or
in standby mode.
Bit:
Initial value:
R/W:
31
30
29
28
27
— DMAIW2 DMAIW1 DMAIW0 —
0
1
1
1
0
R
R/W
R/W
R/W
R
26
A6IW2
1
R/W
25
A6IW1
1
R/W
24
A6IW0
1
R/W
Bit: 23
22
21
20
19
18
17
16
—
A5IW2 A5IW1 A5IW0
—
A4IW2 A4IW1 A4IW0
Initial value: 0
1
1
1
0
1
1
1
R/W: R
R/W
R/W
R/W
R
R/W
R/W
R/W
Bit: 15
14
13
12
11
10
9
8
—
A3IW2 A3IW1 A3IW0
—
A2IW2 A2IW1 A2IW0
Initial value: 0
1
1
1
0
1
1
1
R/W: R
R/W
R/W
R/W
R
R/W
R/W
R/W
Bit: 7
6
5
4
3
2
1
0
—
A1IW2 A1IW1 A1IW0
—
A0IW2 A0IW1 A0IW0
Initial value: 0
1
1
1
0
1
1
1
R/W: R
R/W
R/W
R/W
R
R/W
R/W
R/W
Bits 31, 27, 23, 19, 15, 11, 7, and 3—Reserved: These bits are always read as 0, and the write
value should always be 0.
Bits 30 to 28— DMAIW-DACK Device Inter-Cycle Idle Specification (DMAIW2–
DMAIW0): These bits specify the number of idle cycles between bus cycles to be inserted when
switching from a DACK device to another space, or from a read access to a write access on the
Rev. 3.0, 04/02, page 331 of 1064