HD6417751 Datasheet, PDF (425/1105 Pages) Renesas Technology Corp – SuperH RISC engine

CKIO
Address
RD/
Tpc Tr1 Tr2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2
Row
c1
c2
c8
D31–D0
(read)
D31–D0
(write)
d1
d2
d1
d2
d8
d8
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.19(1) DRAM Burst Bus Cycle, RAS Down Mode Start
(Fast Page Mode, RCD = 0, AnW = 0)
Rev. 3.0, 04/02, page 385 of 1064