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| HD6417751 Datasheet, PDF (1029/1105 Pages) Renesas Technology Corp – SuperH RISC engine | |||
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CKIO
Bank
TRp1 TRp2 TRp3 TRp4 TMw TMw2 TMw3 TMw4 TMw5
tAD
tAD
tAD
Precharge-sel
Address
RD/
tCSD tCSD
tRWD
tRASD
tRWD
tRASD
tCSD
tRWD
tRASD
DQMn
D31âD0
(write)
tCASD2
tDQMD
tWDD
tCASD2
tCASD2
tCASD2
tDQMD
tWDD
tBSD
CKE
DACKn
tDACD
tDACD
Notes: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
Figure 23.34(a) Synchronous DRAM Bus Cycle: Mode Register Setting (PALL)
Rev. 3.0, 04/02, page 989 of 1064
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