HD6417751 Datasheet, PDF (778/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Table 19.4 Interrupt Exception Handling Sources and Priority Order (cont)
Interrupt Source
PCIC (0) PCISERR
PCIC (1) PCIERR
PCIPWDWN
PCIPWON
PCIDMA0
PCIDMA1
PCIDMA2
PCIDMA3
TMU3 TUNI3
TMU4 TUNI4
TMU0
TMU1
TMU2
RTC
SCI
SCIF
WDT
REF
TUNI0
TUNI1
TUNI2
TICPI2
ATI
PRI
CUI
ERI
RXI
TXI
TEI
ERI
RXI
BRI
TXI
ITI
RCMI
INTEVT Interrupt Priority IPR (Bit
Code (Initial Value) Numbers)
Priority within
IPR Setting Unit
H'A00 15–0 (0)
INTPRI00 —
(3–0)
H'AE0
H'AC0
H'AA0
H'A80
H'A60
H'A40
H'A20
15–0 (0)
INTPRI00
(7–4)
High
↑






↓
Low
H'B00 15–0 (0)
INTPRI00 —
(11–8)
H'B80 15–0 (0)
INTPRI00 —
(15–12)
H'400 15–0 (0)
IPRA (15–12) —
H'420 15–0 (0)
IPRA (11–8) —
H'440 15–0 (0)
IPRA (7–4) High
H'460
Low
H'480
H'4A0
H'4C0
15–0 (0)
IPRA (3–0)
High
↑↓
Low
H'4E0
H'500
H'520
H'540
15–0 (0)
IPRB (7–4)
High
↑


↓
Low
H'700
H'720
H'740
H'760
15–0 (0)
IPRC (7–4)
High
↑


↓
Low
H'560 15–0 (0)
IPRB (15–12) —
H'580 15–0 (0)
IPRB (11–8) High
ROVI
H'5A0
Low
Notes: * SH7751R only
TUNI0–TUNI4: Underflow interrupts
TICPI2: Input capture interrupt
Default
Priority
High
↑














































↓
Low
Rev. 3.0, 04/02, page 738 of 1064