HD6417751 Datasheet, PDF (1044/1105 Pages) Renesas Technology Corp – SuperH RISC engine

CKIO
A25–A0
RD/
D31–D0
(write)
TRr1
TRr2
TRr3
TRr4 TRr4w TRr5
Trc
Trc
Trc
t_AD
t_CSD
t_RWD
t_RASD
t_RASD
t_CASD1
t_CASD1
t_WDD
t_RASD
t_CASD1
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
t_DACD
t_DACD
Notes: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
Figure 23.48 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh
(TRAS [2:0] = 001, TRC [2:0] = 001)
Rev. 3.0, 04/02, page 1004 of 1064