HD6417751 Datasheet, PDF (257/1105 Pages) Renesas Technology Corp – SuperH RISC engine

9.1.2 Register Configuration
Table 9.2 shows the registers used for power-down mode control.
Table 9.2 Power-Down Mode Registers
Name
Abbreviation R/W
Standby control STBCR
R/W
register
Standby control STBCR2
R/W
register 2
Clock stop register CLKSTP00
R/W
Clock stop clear
register
CLKSTPCLR00 W
Area 7
Initial Value P4 Address Address
Access
Size
H'00
H'FFC00004 H'1FC00004 8
H'00
H'FFC00010 H'1FC00010 8
H'00000000 H'FE0A0000 H'1E0A0000 32
H'00000000 H'FE0A0008 H'1E0A0008 32
9.1.3 Pin Configuration
Table 9.3 shows the pins used for power-down mode control.
Table 9.3 Power-Down Mode Pins
Pin Name
Processor status 1
Processor status 0
Abbreviation
STATUS1
STATUS0
I/O
Output
Sleep request
6/((3
Hardware standby
CA
request
Notes: H: High level
L: Low level
Input
Input
Function
Indicate the processor’s operating status
(STATUS1, STATUS0).
HH: Reset
HL: Sleep mode
LH: Standby mode
LL: Normal operation
A transition to sleep mode is effected by
inputting a low-level to the pin.
A transition to hardware standby mode is
effected by inputting a low-level to the
pin.
Rev. 3.0, 04/02, page 217 of 1064