HD6417751 Datasheet, PDF (715/1105 Pages) Renesas Technology Corp – SuperH RISC engine

16.4 SCIF Interrupt Sources and the DMAC
The SCIF has four interrupt sources: transmit-FIFO-data-empty interrupt (TXI) request, receive-
error interrupt (ERI) request, receive-FIFO-data-full interrupt (RXI) request, and break interrupt
(BRI) request.
Table 16.6 shows the interrupt sources and their order of priority. The interrupt sources are
enabled or disabled by means of the TIE, RIE, and REIE bits in SCSCR2. A separate interrupt
request is sent to the interrupt controller for each of these interrupt sources.
When transmission/reception is carried out using the DMAC, output of interrupt requests to the
interrupt controller can be inhibited by clearing the RIE bit in SCSCR2 to 0. By setting the REIE
bit to 1 while the RIE bit is cleared to 0, it is possible to output ERI and BRI interrupt requests, but
not RXI interrupt requests.
When the TDFE flag in the serial status register (SCFSR2) is set to 1, a transmit-FIFO-data-empty
request is generated separately from the interrupt request. A transmit-FIFO-data-empty request
can activate the DMAC to perform data transfer.
When the RDF flag or DR flag in SCFSR2 is set to 1, a receive-FIFO-data-full request is
generated separately from the interrupt request. A receive-FIFO-data-full request can activate the
DMAC to perform data transfer.
When using the DMAC for transmission/reception, set and enable the DMAC before making the
SCIF settings. See section 14, Direct Memory Access Controller (DMAC), for details of the
DMAC setting procedure.
When the BRK flag in SCFSR2 or the ORER flag in the line status register (SCLSR2) is set to 1, a
BRI interrupt request is generated.
The TXI interrupt indicates that transmit data can be written, and the RXI interrupt indicates that
there is receive data in SCFRDR2.
Table 16.6 SCIF Interrupt Sources
Interrupt
Source
ERI
RXI
BRI
TXI
Description
DMAC
Activation
Interrupt initiated by receive error flag (ER)
Not possible
Interrupt initiated by receive FIFO data full flag Possible
(RDF) or receive data ready flag (DR)
Interrupt initiated by break flag (BRK) or overrun Not possible
error flag (ORER)
Interrupt initiated by transmit FIFO data empty Possible
flag (TDFE)
Priority on
Reset Release
High
↑
↓
Low
Rev. 3.0, 04/02, page 675 of 1064