HD6417751 Datasheet, PDF (390/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bit 0—EDO Mode (EDOMODE): Used to specify the data sampling timing for data reads when
using EDO mode DRAM interface. The setting of this bit does not affect the operation timing of
memory other than DRAM. Set this bit to 1 only when DRAM is used.
13.2.9 PCMCIA Control Register (PCR)
The PCMCIA control register (PCR) is a 16-bit readable/writable register that specifies the 2(
and :( signal assertion/negation timing for the PCMCIA interface connected to areas 5 and 6.
The 2( and :( signal assertion width is set by the wait control bits in the WCR2 register.
PCR is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in
standby mode.
Bit: 15
14
13
12
11
10
9
8
Bit name: A5PCW1 A5PCW0 A6PCW1 A6PCW0 A5TED2 A5TED1 A5TED0 A6TED2
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit: 7
6
5
4
3
2
1
0
Bit name: A6TED1 A6TED0 A5TEH2 A5TEH1 A5TEH0 A6TEH2 A6TEH1 A6TEH0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits 15 and 14—PCMCIA Wait (A5PCW1, A5PCW0): These bits specify the number of waits
to be added to the number of waits specified by WCR2 in a low-speed PCMCIA wait cycle. The
setting of these bits is selected when the PCMCIA interface access TC bit is 0.
Bit 15: A5PCW1
0
1
Bit 14: A5PCW0
0
1
0
1
Waits Inserted
0 (Initial value)
15
30
50
Bits 13 and 12—PCMCIA Wait (A6PCW1, A6PCW0): These bits specify the number of waits
to be added to the number of waits specified by WCR2 in a low-speed PCMCIA wait cycle. The
setting of these bits is selected when the PCMCIA interface access TC bit is 0.
Rev. 3.0, 04/02, page 350 of 1064