HD6417751 Datasheet, PDF (880/1105 Pages) Renesas Technology Corp – SuperH RISC engine

This register can be written to only when bits 31 to 24 are H'A5.
Always set bit 0 (CFINIT) to 1 on completion of PCIC register initialization.
Bits 31 to 10—Reserved: These bits are always read as 0. When writing, write H'A5 to bits 31 to
24, and 0 to others.
Bit 9—Target Read Single Buffer (TRDSGL): This bit specifies whether one target read buffer
(32 bytes) or two target read buffers (64 bytes) are used for target memory read access to the
PCIC. When two target read buffers faces are used, the data from two buffers are read via the local
bus in advanced.
Bit 9: TRDSGL
0
1
Description
Use 2 target read buffers
Use 1 target read buffer only
(Initial value)
Bit 8—Data Byte Swap (BYTESWAP): Specifies whether the data byte is swapped when the
PCIC performs PIO transfer.
Bit 8: BYTESWAP Description
0
Send data as-is
1
Swap data byte before sending
Note: For details, refer to section 22.4, Endians.
(Initial value)
Bit 7—PCI Signal Pull-up (PCIUP): Controls the pull-up resistance of the PCI signal. Regarding
the pins that are subject to pull-up, refer to Table 22.1. Regarding the pull-up control provided
when the 3&,3(4/MD9, 3&,5(4/MD10 or 3&,5(4 is used as a port, refer to the section on
port control register (PCIPCTR).
Bit 7: PCIUP
0
1
Description
Pull-up
No pull-up
(Initial value)
Bit 6—Bus Master Arbitration (BMABT): Controls the PCI bus arbitration mode of the PCIC
when the PCIC is operating as the host. When the PCIC is non-host, the value of this bit is
ignored.
Bit 6: BMABT
0
1
Description
Fixed priority order (device 0 (PCIC) > device 1 > device 2 > device 3 >
device 4)
(Initial value)
Pseudo round-ribbon (The priority level of the device with bus privileges is
set lowest at the next access.)
Rev. 3.0, 04/02, page 840 of 1064