HD6417751 Datasheet, PDF (798/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bits 5 and 4—Instruction Access/Operand Access Select A (IDA1, IDA0): These bits specify
whether an instruction access cycle or an operand access cycle is used as the bus cycle in the
channel A break conditions.
Bit 5: IDA1
0
1
Bit 4: IDA0
0
1
0
1
Description
Condition comparison is not performed
(Initial value)
Instruction access cycle is used as break condition
Operand access cycle is used as break condition
Instruction access cycle or operand access cycle is used as
break condition
Bits 3 and 2—Read/Write Select A (RWA1, RWA0): These bits specify whether a read cycle or
write cycle is used as the bus cycle in the channel A break conditions.
Bit 3: RWA1
0
1
Bit 2: RWA0
0
1
0
1
Description
Condition comparison is not performed
(Initial value)
Read cycle is used as break condition
Write cycle is used as break condition
Read cycle or write cycle is used as break condition
Bits 6, 1, and 0—Operand Size Select A (SZA2–SZA0): These bits select the operand size of
the bus cycle used as a channel A break condition.
Bit 6: SZA2 Bit 1: SZA1
0
0
1
1
0
1
Note: *: Don’t care
Bit 0: SZA0
0
1
0
1
0
1
*
Description
Operand size is not included in break conditions
(Initial value)
Byte access is used as break condition
Word access is used as break condition
Longword access is used as break condition
Quadword access is used as break condition
Reserved (cannot be set)
Reserved (cannot be set)
Rev. 3.0, 04/02, page 758 of 1064