HD6417751 Datasheet, PDF (694/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bit 0—Loopback Test (LOOP): Internally connects the transmit output pin (TxD2) and receive
input pin (RxD2), and the #%$ pin and %$ pin, enabling loopback testing.
Bit 0: LOOP
0
1
Description
Loopback test disabled
Loopback test enabled
(Initial value)
16.2.10 FIFO Data Count Register (SCFDR2)
SCFDR2 is a 16-bit register that indicates the number of data bytes stored in SCFTDR2 and
SCFRDR2.
The upper 8 bits show the number of transmit data bytes in SCFTDR2, and the lower 8 bits show
the number of receive data bytes in SCFRDR2.
SCFDR2 can be read by the CPU at all times.
Bit: 15
14
13
12
11
10
9
8
—
—
—
T4
T3
T2
T1
T0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
These bits show the number of untransmitted data bytes in SCFTDR2. A value of H'00 indicates
that there is no transmit data, and a value of H'10 indicates that SCFTDR2 is full of transmit data.
Bit: 7
6
5
4
3
2
1
0
—
—
—
R4
R3
R2
R1
R0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
These bits show the number of receive data bytes in SCFRDR2. A value of H'00 indicates that
there is no receive data, and a value of H'10 indicates that SCFRDR2 is full of receive data.
Rev. 3.0, 04/02, page 654 of 1064