HD6417751 Datasheet, PDF (434/1105 Pages) Renesas Technology Corp – SuperH RISC engine

little-endian mode, DQM3 specifies an access to address 4n + 3, and DQM0 specifies an access to
address 4n.
Figure 13.23 shows examples of the connection of 16M × 16-bit synchronous DRAMs.
SH7751 Series
A11–A2
CKIO
CKE
512k × 16-bit × 2-bank
synchronous DRAM
A9–A0
CLK
CKE
RD/
D31–D16
DQM3
DQM2
I/O15–I/O0
DQMU
DQML
A9–A0
CLK
CKE
D15–D0
DQM1
DQM0
I/O15–I/O0
DQMU
DQML
Figure 13.23 Example of 32-Bit Data Width Synchronous DRAM Connection (Area 3)
Address Multiplexing: Synchronous DRAM can be connected without external multiplexing
circuitry in accordance with the address multiplex specification bits AMXEXT and AMX2–
AMX0 in MCR. Table 13.15 shows the relationship between the address multiplex specification
bits and the bits output at the address pins. See Appendix E, Synchronous DRAM Address
Multiplexing Tables.
The address signals output at address pins A25–A18, A1, and A0 are not guaranteed.
When A0, the LSB of the synchronous DRAM address, is connected to the SH7751 Series, it
makes a longword address specification. Connection should therefore be made in this order:
connect pin A0 of the synchronous DRAM to pin A2 of the SH7751 Series, then connect pin A1
to pin A3.
Rev. 3.0, 04/02, page 394 of 1064