HD6417751 Datasheet, PDF (95/1105 Pages) Renesas Technology Corp – SuperH RISC engine

3.2 Register Descriptions
There are six MMU-related registers.
1. PTEH
31
VPN
10 9 8 7
0
——
ASID
2. PTEL
31 30 29 28
———
3. PTEA
31
4. TTB
31
5. TEA
31
PPN
10 9 8 7 6 5 4 3 2 1 0
— V SZ PR SZ C D SH WT
432
0
TC SA
0
TTB
0
Virtual address at which MMU exception or address error occurred
6. MMUCR
31
26 25 24 23
LRUI
——
URB
18 17 16 15
——
URC
10 9 8 7 6 5 4 3 2 1 0
SV — — — — — TI — AT
SQMD
— indicates a reserved bit: the write value must be 0, and a read will return 0.
Figure 3.2 MMU-Related Registers
Rev. 3.0, 04/02, page 55 of 1064