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HD6417751 Datasheet, PDF (693/1105 Pages) Renesas Technology Corp – SuperH RISC engine | |||
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Bits 5 and 4âTransmit FIFO Data Number Trigger (TTRG1, TTRG0): These bits are used
to set the number of remaining transmit data bytes that sets the transmit FIFO data register empty
(TDFE) flag in the serial status register (SCFSR2). The TDFE flag is set when the number of
transmit data bytes in SCFTDR2 is equal to or less than the trigger set number shown in the
following table.
Bit 5: TTRG1
Bit 4: TTRG0
Transmit Trigger Number
0
0
8 (8)
(Initial value)
1
4 (12)
1
0
2 (14)
1
1 (15)
Note: Figures in parentheses are the number of empty bytes in SCFTDR2 when the flag is set.
Bit 3âModem Control Enable (MCE): Enables the %$ and #%$ modem control signals.
Bit 3: MCE
Description
0
Modem signals disabled*
(Initial value)
1
Modem signals enabled
Note: * %$ is fixed at active-0 regardless of the input value, and #%$ output is also fixed at 0.
Bit 2âTransmit FIFO Data Register Reset (TFRST): Invalidates the transmit data in the
transmit FIFO data register and resets it to the empty state.
Bit 2: TFRST
Description
0
Reset operation disabled*
(Initial value)
1
Reset operation enabled
Note: * A reset operation is performed in the event of a power-on reset or manual reset.
Bit 1âReceive FIFO Data Register Reset (RFRST): Invalidates the receive data in the receive
FIFO data register and resets it to the empty state.
Bit 1: RFRST
Description
0
Reset operation disabled*
(Initial value)
1
Reset operation enabled
Note: * A reset operation is performed in the event of a power-on reset or manual reset.
Rev. 3.0, 04/02, page 653 of 1064
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