HD6417751 Datasheet, PDF (278/1105 Pages) Renesas Technology Corp – SuperH RISC engine

9.9.5 Hardware Standby Mode Timing
Figure 9.12 shows the timing of the signals of the respective pins in hardware standby mode.
The CA pin level must be kept low while in hardware standby mode.
After setting the 5(6(7 pin level low, the clock starts when the CA pin level is switched to high.
CKIO
CA
STATUS
Normal^*1
Standby^*2 Undefined Reset
0–10 Bcyc
Waiting for end of bus cycle
0–10 Bcyc
Notes: *1 Same at sleep and reset
*2 High impedance when STBCR2. STHZ = 0
Figure 9.12 Hardware Standby Mode Timing
(When CA = Low in Normal Operation)
Rev. 3.0, 04/02, page 238 of 1064