HD6417751 Datasheet, PDF (990/1105 Pages) Renesas Technology Corp – SuperH RISC engine

23.3.1 Clock and Control Signal Timing
Table 23.18 Clock and Control Signal Timing (HD6417751RBP240)
V_DDQ = 3.0 to 3.6 V, V_DD = 1.5 V, Ta = –20 to 75°C, C_L = 30 pF
Item
Symbol Min
Max
Unit Figure
EXTAL
PLL1 6-times/PLL2 operation
f_EX
clock input _{PLL1 12-times/PLL2 operation}
frequency
PLL1/PLL2 not operating
16
34
MHz
14
20
1
34
EXTAL clock input cycle time
EXTAL clock input low-level pulse width
EXTAL clock input high-level pulse width
EXTAL clock input rise time
EXTAL clock input fall time
CKIO clock
output
PLL1/PLL2 operating
PLL1/PLL2 not operating
t_EXcyc
30
1000 ns
23.1
t_EXL
3.5
—
ns
23.1
t_EXH
3.5
—
ns
23.1
t_EXr
—
4
ns
23.1
t_EXf
—
4
ns
23.1
f_OP
25
120
MHz
1
34
MHz
CKIO clock output cycle time
t_cyc
8.3
CKIO clock output low-level pulse width
t_CKOL1
1
CKIO clock output high-level pulse width
t_CKOH1
1
CKIO clock output rise time
t_CKOr
—
CKIO clock output fall time
t_CKOf
—
CKIO clock output low-level pulse width
t_CKOL2
3
CKIO clock output high-level pulse width
t_CKOH2
3
Power-on oscillation settling time
t_OSC1
10
Power-on oscillation settling time/mode settling t_OSCMD
10
MD reset setup time
t_MDRS
3
MD reset hold time
#$% assert time
t_MDRH
20
t_RESW
20
1000 ns
23.2(1)
—
ns
23.2(1)
—
ns
23.2(1)
3
ns
23.2(1)
3
ns
23.2(1)
—
ns
23.2(2)
—
ns
23.2(2)
—
ms 23.3, 23.5
—
ms 23.3, 23.5
—
t_cyc
—
ns
23.3, 23.5
—
t_cyc
23.3, 23.4, 23.5,
23.6
PLL synchronization settling time
t_PLL
200
—
µs
23.9, 23.10
Standby return oscillation settling time 1
t_OSC2
3
—
ms 23.4, 23.6
Standby return oscillation settling time 2
t_OSC3
3
—
ms 23.7
Standby return oscillation settling time 3
t_OSC4
3
—
ms 23.8
Standby return oscillation settling time 1*
t_OSC2
2
—
ms
Standby return oscillation settling time 2*
t_OSC3
2
—
ms
Standby return oscillation settling time 3*
t_OSC4
2
—
ms
IRL interrupt determination time
(RTC used, standby mode)
t_IRLSTB
—
200
µs
23.10
%#$% reset hold time
t_TRSTRH
0
—
ns
23.3, 23.5
Notes: 1. When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 34 MHz.
When a 3rd overtone crystal resonator is used, an external tank circuit is necessary.
2. As there is feedback from the CKIO pin when PLL2 is operating, the load capacitance connected
to the CKIO pin should be a maximum of 50 pF.
* When the oscillation settling time of the crystal resonator is 1 ms or less.
Rev. 3.0, 04/02, page 950 of 1064