HD6417751 Datasheet, PDF (762/1105 Pages) Renesas Technology Corp – SuperH RISC engine

18.2.4 Port Data Register B (PDTRB)
Port data register B (PDTRB) is a 16-bit readable/writable register used as a data latch for each bit
in the 16-bit port B. When a bit is set as an output, the value written to the PDTRB register is
output from the external pin. When a value is read from the PDTRB register while a bit is set as an
input, the external pin value sampled on the external bus clock is read. When a bit is set as an
output, the value written to the PDTRB register is read.
PDTRB is not initialized by a power-on or manual reset, or in standby mode, and retains its
contents.
Bit: 15
14
13
12
11
10
9
8
PB31DT PB30DT PB29DT PB28DT PB27DT PB26DT PB25DT PB24DT
Initial value: —
—
—
—
—
—
—
—
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit: 7
6
5
4
3
2
1
0
PB23DT PB22DT PB21DT PB20DT PB19DT PB18DT PB17DT PB16DT
Initial value: —
—
—
—
—
—
—
—
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
18.2.5 GPIO Interrupt Control Register (GPIOIC)
The GPIO interrupt control register (GPIOIC) is a 16-bit readable/writable register that performs
16-bit interrupt input control.
GPIOIC is initialized to H'0000 by a power-on reset. It is not initialized by a manual reset or in
standby mode, and retains its contents.
GPIO interrupts are active-low level interrupts. Bit-by-bit masking is possible, and the OR of all
the bits set as GPIO interrupts is used for interrupt detection. Which bits interrupts are input to can
be identified by reading the PDTRA register.
Rev. 3.0, 04/02, page 722 of 1064