HD6417751 Datasheet, PDF (884/1105 Pages) Renesas Technology Corp – SuperH RISC engine

22.2.19 PCI Local Address Register [1:0] (PCILAR [1:0])
Bit: 31
30
29
28
27
26
25
24
—
—
—
LAR28 LAR27 LAR26 LAR25 LAR24
Initial value: 0
0
0
0
0
0
0
0
PCI-R/W: R
R
R
R
R
R
R
R
PP Bus-R/W: R
R
R
R/W
R/W
R/W
R/W
R/W
Bit: 23
22
21
20
19
18
17
16
LAR23 LAR22 LAR21 LAR20
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
PCI-R/W: R
R
R
R
R
R
R
R
PP Bus-R/W: R/W
R/W
R/W
R/W
R
R
R
R
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
PCI-R/W: R
R
R
R
R
R
R
R
PP Bus-R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
PCI-R/W: R
R
R
R
R
R
R
R
PP Bus-R/W: R
R
R
R
R
R
R
R
The PCI local address register [1:0] (PCILAR [1:0]) specifies the starting address (external
address of local bus) of the two local address spaces (address space 0 and address space 1)
supported when performing memory read/memory write operations due to target transfers to the
PCIC. It is a 32-bit register that can be read and written from the PP bus and is read-only from the
PCI bus.
The PCILAR [1:0] register is initialized to H'00000000 at a power-on reset and software reset.
The valid bits of the local address specified by this register vary according to the capacity of the
address space specified in the PCILSR [1:0] register. In other words, set 0 in the least significant
address bit which corresponds to the capacity set by PCILSR0, 1, and set the starting address only
in the most significant address bit. For example, when the capacity of the local address space is set
to 32MB (PCILSR: H'01F00000), bits 28 to 25 of the local address are valid. Only the value set in
these bits is used as the physical address of the local address space.
Rev. 3.0, 04/02, page 844 of 1064