HD6417751 Datasheet, PDF (909/1105 Pages) Renesas Technology Corp – SuperH RISC engine

The I/O space base register (PCIIOBR) species the most significant 14 bits of the address of the
PCI I/O space when performing I/O read and I/O write operations by PIO transfer. It also specifies
locked transfers. This 32-bit read/write register can be accessed from the PP bus.
All bits of the PCII0BR register are initialized to 0 at a power-on reset. They are not initialized at
a software reset.
Setting bit 0 (LOCK) to 1 locks the I/O space for PIO transfers while the bit remains set. A locked
transfer consists of the combined read and write operations. Do not attempt to perform other PIO
transfers during the locked combination of read and write operations.
Always write to this register prior to I/O space read and I/O space write operations by PIO
transfer.
Bits 31 to 18—I/O Space Base Address (IOBR31 to 18): Sets the base register for the PCI I/O
space in PIO transfers.
Bits 17 to 1—Reserved: These bits always return 0 when read. Always write 0 to these bits when
writing.
Bit 0—Lock Transfer (LOCK): Specifies the locking of the I/O space during PIO transfer.
Bit 0: LOCK
0
1
Description
Not locked
Locked
(Initial value)
Rev. 3.0, 04/02, page 869 of 1064