HD6417751 Datasheet, PDF (349/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Table 13.1 BSC Pins (cont)
Name
Signals
I/O
Column address &$6/DQM0 O
strobe 0
Column address &$6/DQM1 O
strobe 1
Column address &$6/DQM2 O
strobe 2
Column address &$6/DQM3 O
strobe 3
Ready
Area 0 MPX
interface
specification/
16-bit I/O
5'<
I
MD6/,2,6 I
Clock enable
Bus release
request
Bus use
permission
Area 0 bus
width/PCMCIA
card select
CKE
O
%5(4/
I
%6$&.
%$&./
O
%65(4
MD3/&($*¹ I/O
MD4/&(%*²
Endian switchover MD5
I
Master/slave
switchover
MD7/&76
I/O
DMAC0
DACK0
O
acknowledge
signal
DMAC1
DACK1
O
acknowledge
signal
Description
When setting DRAM interface: &$6 signal for
D7–D0
When setting synchronous DRAM interface:
selection signal for D7–D0
When setting DRAM interface: &$6 signal for
D15–D8
When setting synchronous DRAM interface:
selection signal for D15–D8
When setting DRAM interface: &$6 signal for
D23–D16
When setting synchronous DRAM interface:
selection signal for D23–D16
When setting DRAM interface: &$6 signal for
D31–D24
When setting synchronous DRAM interface:
selection signal for D31–D24
Wait state request signal
In power-on reset: Designates area 0 bus as MPX
interface (1: SRAM, 0: MPX)
When setting PCMCIA interface: 16-bit I/O
designation signal. Valid only in little-endian mode.
Synchronous DRAM clock enable control signal
Bus release request signal/bus acknowledge signal
Bus use permission signal/bus request
In power-on reset: area 0 bus width specification
signal
When using PCMCIA: &($, &(%
Endian specification in a power-on reset
Indicates master/slave status in a power-on reset
Serial interface &76
DMAC channel 0 data acknowledge
DMAC channel 1 data acknowledge
Rev. 3.0, 04/02, page 309 of 1064