HD6417751 Datasheet, PDF (1021/1105 Pages) Renesas Technology Corp – SuperH RISC engine

CKIO
Bank
Precharge-sel
Address
RD/
Tr
Trw
Tc1
Tc2
Tc3
Tc4
Trwl
Trwl
Tpc
t_AD
Row
Row
t_AD
H/L
Row
c1
t_CSD
t_RWD t_RWD
t_RASD t_RASD
t_AD
t_CSD
t_CASD2
t_CASD2
DQMn
D31–D0
(write)
t_DQMD
t_DQMD
t_WDD
t_WDD
c1
t_BSD
t_BSD
CKE
DACKn
(SA: IO → memory)
t_DACD t_DACD
Notes: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
Figure 23.26 Synchronous DRAM Auto-Precharge Write Bus Cycle: Single
(RCD [1:0] = 01, TPC [2:0] = 001, TRWL [2:0] = 010)
Rev. 3.0, 04/02, page 981 of 1064