HD6417751 Datasheet, PDF (132/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Effective address
31
26 25
13 12 11 10 9
543 21 0
OIX
22
[13]
9
0
RAM area
determination
ORA
[12]
[11:5]
Address array
3
Tag
UV
Longword (LW) selection
Data array
LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7
MMU
19
511 19 bits 1 bit 1 bit
32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits
Compare
Read data
Write data
Hit signal
Figure 4.2 Configuration of Operand Cache (SH7751)
Rev. 3.0, 04/02, page 92 of 1064