HD6417751 Datasheet, PDF (379/1105 Pages) Renesas Technology Corp – SuperH RISC engine

• When Synchronous DRAM Interface is Set*¹
Bit 11: A2W2 Bit 10: A2W1 Bit 9: A2W0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
Notes: *1 External wait input is always ignored
*2 Inhibited in RAS down mode
Description
Synchronous DRAM &$6 Latency Cycles
Inhibited
1*²
2
3
4*²
5*²
Inhibited
Inhibited
Bits 8 to 6—Area 1 Wait Control (A1W2–A1W0): These bits specify the number of wait states
to be inserted for area 1. For the case where an MPX interface setting is made, see table 13.7.
Bit 8: A1W2
0
1
Bit 7: A1W1
0
1
0
1
Bit 6: A1W0
0
1
0
1
0
1
0
1
Description
Inserted Wait States
5'< Pin
0
Ignored
1
Enabled
2
Enabled
3
Enabled
6
Enabled
9
Enabled
12
Enabled
15 (Initial value)
Enabled
Rev. 3.0, 04/02, page 339 of 1064