HD6417751 Datasheet, PDF (741/1105 Pages) Renesas Technology Corp – SuperH RISC engine

17.4 Usage Notes
The following points should be noted when using the SCI as a smart card interface.
(1) Receive Data Sampling Timing and Receive Margin
In asynchronous mode, the SCI operates on a base clock with a frequency of 372 times the transfer
rate. In reception, the SCI synchronizes internally with the fall of the start bit, which it samples on
the base clock. Receive data is latched at the rising edge of the 186th base clock pulse. The timing
is shown in figure 17.10.
372 clocks
186 clocks
0
185
371 0
185
371 0
Base clock
Receive data
(RxD)
Synchronization
sampling timing
Start
bit
D0
D1
Data sampling
timing
Figure 17.10 Receive Data Sampling Timing in Smart Card Mode
The receive margin in smart card mode can therefore be expressed as shown in the following
equation.
M = (0.5 – ¹ ) – (L – 0.5) F – ^{| D – 0.5 |} (1 + F) × 100%
2N
N
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 372)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L =10)
F: Absolute deviation of clock frequency
Rev. 3.0, 04/02, page 701 of 1064