HD6417751 Datasheet, PDF (960/1105 Pages) Renesas Technology Corp – SuperH RISC engine

22.6 Interrupts
22.6.1 Interrupts from PCIC to CPU
There are 8 interrupts, as shown in the following, that can be generated by the PCIC for the CPU.
The interrupt controller also controls the individual interrupt priority levels and interrupt masks,
etc. See the section 19, Interrupt Controller (INTC), for details.
Table 22.13 Interrupts
Interrupt Source
PCISERR
PCIERR
PCIPWDWN
PCIPWON
PCIDMA0
PCIDMA1
PCIDMA2
PCIDMA3
Function
SERR error interrupt
ERR error interrupt
Power-down request interrupt
Power-on request interrupt
DMA0 transfer end interrupt
DMA1 transfer end interrupt
DMA2 transfer end interrupt
DMA3 transfer end interrupt
INTPRI00
[3:0]
[7:4]
Priority
High
High
Low
Low
System Error (6(55) Interrupt (PCISERR): This interrupt shows detection of the 6(55 pin
being asserted. This interrupt is generated only when the PCIC is operating as host.
When the PCIC is operating as non-host, the SERR bit in the PCI control register (PCICR) is used
to notify the host device of the system error (assertion of 6(55 pin).
The 6(55 pin can be asserted when the SERR bit is asserted and when an address parity error is
detected in a target transfer.
When the SER bit of the PCI configuration register 1 (PCICONF1) is set to 0, the 6(55 pin is not
asserted.
Error Interrupt (PCIERR): Shows error detection by the PCIC. The error interrupt is asserted
when either of the following errors is detected:
• Interrupts detected by PCI interrupt register (PCIINT)
• Interrupts detected by PCI arbiter interrupt register (PCIAINT)
The interrupts that can be detected by these two registers can also be masked. The PCI interrupt
mask register (PCIINTM) masks the PCIINT interrupts, and the PCI arbiter interrupt mask register
(PCIAINTM) masks the PCIAINT interrupts. See section 22.2, PCIC Register Descriptions, for
details.
Rev. 3.0, 04/02, page 920 of 1064