HD6417751 Datasheet, PDF (377/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bits 19 to 17—Area 4 Wait Control (A4W2–A4W0): These bits specify the number of wait
states to be inserted for area 4. For the case where an MPX interface setting is made, see table
13.7.
Bit 19: A4W2
0
1
Bit 18: A4W1
0
1
0
1
Bit 17: A4W0
0
1
0
1
0
1
0
1
Description
Inserted Wait States 5'< Pin
0
Ignored
1
Enabled
2
Enabled
3
Enabled
6
Enabled
9
Enabled
12
Enabled
15 (Initial value)
Enabled
Bits 16 and 12—Reserved: These bits are always read as 0, and should only be written with 0.
Bits 15 to 13—Area 3 Wait Control (A3W2–A3W0): These bits specify the number of wait
states to be inserted for area 3. External wait input is only enabled when the SRAM interface or
MPX interface is used, and is ignored when DRAM or synchronous DRAM is used. For the case
where an MPX interface setting is made, see table 13.7.
• When SRAM Interface is Set
Bit 15: A3W2
0
1
Bit 14: A3W1
0
1
0
1
Bit 13: A3W0
0
1
0
1
0
1
0
1
Description
Inserted Wait States 5'< Pin
0
Ignored
1
Enabled
2
Enabled
3
Enabled
6
Enabled
9
Enabled
12
Enabled
15 (Initial value)
Enabled
Rev. 3.0, 04/02, page 337 of 1064