HD6417751 Datasheet, PDF (819/1105 Pages) Renesas Technology Corp – SuperH RISC engine

21.1.3 Pin Configuration
Table 21.1 shows the H-UDI pin configuration.
Table 21.1 H-UDI Pins
Pin Name Abbreviation I/O
Function
When Not Used
Clock pin TCK
Input
Same as the JTAG serial clock input Open*¹
pin. Data is transferred from data
input pin TDI to the H-UDI circuit, and
data is read from data output pin
TDO, in synchronization with this
signal.
Mode pin TMS
Input
The mode select input pin. Changing
this signal in synchronization with
TCK determines the meaning of the
data input from TDI. The protocol
conforms to the JTAG (IEEE Std
1149.1) specification.
Open*¹
Reset pin 7567
Input
The input pin that resets the H-UDI. *^2, *³
This signal is received
asynchronously with respect to TCK,
and effects a reset of the JTAG
interface circuit when low. 7567 must
be driven low for a certain period
when powering on, regardless of
whether or not JTAG is used. This
differs from the IEEE specification.
Data input TDI
pin
Input
The data input pin. Data is sent to
the H-UDI circuit by changing this
signal in synchronization with TCK.
Open*¹
Data output TDO
pin
Output
The data output pin. Data is sent to
the H-UDI circuit by reading this
signal in synchronization with TCK.
Open
Emulator pin $6(%5./
BRKACK
Input/ Dedicated emulator pin
output
Open*¹
AUDSYNC Output Dedicated emulator pin
Open
AUDCK
AUDATA3–
AUDATA0
Notes: *1 Pulled up inside the chip. When designing a board that allows use of an emulator, or
when using interrupts and resets via the H-UDI, there is no problem in connecting a
pullup resistance externally.
*2 When designing a board that enables the use of an emulator, or when using interrupts
and resets via the H-UDI, drive 7567 low for a period overlapping 5(6(7 at power-on,
and also provide for control by 7567 alone.
Rev. 3.0, 04/02, page 779 of 1064