HD6417751 Datasheet, PDF (890/1105 Pages) Renesas Technology Corp – SuperH RISC engine

22.2.22 PCI Address Data Register at Error (PCIALR)
Bit: 31
30
29
28
27
26
25
24
ALOG31 ALOG30 ALOG29 ALOG28 ALOG27 ALOG26 ALOG25 ALOG24
Initial value: —
—
—
—
—
—
—
—
PCI-R/W: R
R
R
R
R
R
R
R
PP Bus-R/W: R
R
R
R
R
R
R
R
Bit: 23
22
21
20
19
18
17
16
ALOG23 ALOG22 ALOG21 ALOG20 ALOG19 ALOG18 ALOG17 ALOG16
Initial value: —
—
—
—
—
—
—
—
PCI-R/W: R
R
R
R
R
R
R
R
PP Bus-R/W: R
R
R
R
R
R
R
R
Bit: 15
14
13
12
11
10
9
ALOG15 ALOG14 ALOG13 ALOG12 ALOG11 ALOG10 ALOG9
Initial value: —
—
—
—
—
—
—
PCI-R/W: R
R
R
R
R
R
R
PP Bus-R/W: R
R
R
R
R
R
R
8
ALOG8
—
R
R
Bit:
Initial value:
PCI-R/W:
PP Bus-R/W:
7
ALOG7
—
R
R
6
ALOG6
—
R
R
5
ALOG5
—
R
R
4
ALOG4
—
R
R
3
ALOG3
—
R
R
2
ALOG2
—
R
R
1
ALOG1
—
R
R
0
ALOG0
—
R
R
The PCI address data register at error (PCIALR) stores the PCI address data (ALOG [31:0]) of
errors that occur on the PCI bus. It is a 32-bit register that can be read from both the PP bus and
PCI bus.
The PCIALR register is not initialized at a power-on reset or software reset. The initial value is
undefined. A valid value is retained only when one of the PCIINT register bits is set to 1.
The error source holding circuit can only store one error source. For this reason, any second or
subsequent error factors are not stored if errors occur consecutively.
Bits 31 to 0—Address Log (ALOG31 to 0): PIC address data (value of A/D line) at time of error.
(Initial value is undefined.)
Rev. 3.0, 04/02, page 850 of 1064