HD6417751 Datasheet, PDF (432/1105 Pages) Renesas Technology Corp – SuperH RISC engine

CKIO
TRr1 TRr2 TRr3 TRr4
A25–A0
RD/
TRr5 Trc Trc Trc
D63–D0
Figure 13.22 DRAM Self-Refresh Cycle Timing
Power-On Sequence: Regarding use of DRAM after powering on, it is requested that a wait time
(at least 100 µs or 200 µs) during which no access can be performed be provided, followed by at
least the prescribed number (usually 8) of dummy CAS-before-RAS refresh cycles. As the bus
state controller does not perform any special operations for a power-on reset, the necessary power-
on sequence must be carried out by the initialization program executed after a power-on reset.
Rev. 3.0, 04/02, page 392 of 1064