HD6417751 Datasheet, PDF (269/1105 Pages) Renesas Technology Corp – SuperH RISC engine

9.8 Hardware Standby Mode
9.8.1 Transition to Hardware Standby Mode
Setting the CA pin level low effects a transition to hardware standby mode. In this mode, all
modules other than the RTC stop, as in the standby mode selected using the SLEEP command.
Hardware standby mode differs from standby mode as follows:
1. Interrupts and manual resets are not available;
2. All output pins other than the STATUS pin are in the high-impedance state and the pull-up
resistance is off.
3. Even when no power is supplied to power pins other than the RTC power supply pin, the RTC
continues to operate.
The status of the STATUS pin is determined by the STHZ bit of STBCR2. See section D, Pin
Functions, for details of output pin states.
Operation when a low-level is input to the CA pin when in the standby mode depends on the CPG
status, as follows:
1. In standby mode
The clock remains stopped and a transition is made to the hardware standby state.
Interrupts and manual resets are disabled, but the output pins remain in the same state as in
standby mode.
2. When WDT is operating when standby mode is exited by interrupt
Standby mode is momentarily exited, the CPU restarts, and then a transition is made to
hardware standby mode.
Note that the level of the CA pin must be kept low while in hardware standby mode.
9.8.2 Exit from Hardware Standby Mode
In the case of the standby control register and standby control register 2, the module standby
function is exited by writing 0 to the MSTP6–MSTP0 bits. In the case of clock stop register 00,
the module standby function is exited by writing 1 to the corresponding bit in clock stop clear
register 00.
The module standby function is not exited by means of a power-on reset via the 5(6(7 pin or a
power-on reset caused by watchdog timer overflow.
Rev. 3.0, 04/02, page 229 of 1064