HD6417751 Datasheet, PDF (855/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bit 21: 66M
0
1
Description
This device supports 33 MHz operation
This device supports 66 MHz operation
(Initial value)
Bit 20—PCI Power Management (PM): Shows whether the PCI power management is
supported.
Bit 20: PM
0
1
Description
Power management not supported
Power management supported
(Initial value)
Bits 19 to 10—Reserved: These bits always return 0 when read. Always write 0 to these bits.
Bit 9—High-Speed Back-To-Back Control (PBBE): Selects whether or not to allow high-speed
back-to-back control with different targets when privileged as the master.
Bit 9: PBBE
0
1
Description
Allows high-speed back-to-back control only with same target (Initial value)
Allows high-speed back-to-back control with different target (Not supported)
Bit 8—6(55 Output Control (SER): Controls the 6(55 output.
Bit 8: SER
0
1
Description
6(55 output disabled (Hi-Z)
6(55 output enabled
(Initial value)
Bit 7—Wait Cycle Control (WCC): Controls the address/data stepping. When WCC=1, address
and data are output in master write operations, only address is output in master read operations,
and only data is output in target read operations, at least in two clocks.
Bit 7: WCC
0
1
Description
Disable address/data stepping control
Enable address/data stepping control
(Initial value)
Bit 6—Parity Error Response (PER): Controls the device response when a parity error is
detected or a parity error report is received. 3(55 is asserted only when PER = 1.
Rev. 3.0, 04/02, page 815 of 1064