HD6417751 Datasheet, PDF (297/1105 Pages) Renesas Technology Corp – SuperH RISC engine

10.8.3 Notes on Register Access
The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR)
differ from other registers in being more difficult to write to. The procedure for writing to these
registers is given below.
Writing to WTCNT and WTCSR: These registers must be written to with a word transfer
instruction. They cannot be written to with a byte or longword transfer instruction. When writing
to WTCNT, perform the transfer with the upper byte set to H'5A and the lower byte containing the
write data. When writing to WTCSR, perform the transfer with the upper byte set to H'A5 and the
lower byte containing the write data. This transfer procedure writes the lower byte data to
WTCNT or WTCSR. The write formats are shown in figure 10.3.
WTCNT write
15
Address: H'FFC00008
(H'1FC00008)
H'5A
87
0
Write data
WTCSR write
15
Address: H'FFC0000C
(H'1FC0000C)
H'A5
87
0
Write data
Figure 10.3 Writing to WTCNT and WTCSR
Rev. 3.0, 04/02, page 257 of 1064