HD6417751 Datasheet, PDF (394/1105 Pages) Renesas Technology Corp – SuperH RISC engine

For a 32-bit bus:
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Address 0 0 0 0 0 0 0 0 0 LMO LMO LMO WT BL2 BL1 BL0
DE2 DE1 DE0
←→
10 bits set in case of 32-bit bus width
LMODE: RAS-CAS latency
BL:
Burst length
WT:
Wrap type (0: Sequential)
BL
000: Reserved
001: Reserved
010: 4
011: 8*
100: Reserved
101: Reserved
110: Reserved
111: Reserved
LMODE
000: Reserved
001: 1
010: 2
011: 3
100: Reserved
101: Reserved
110: Reserved
111: Reserved
Note: * SH7751R only
13.2.11 Refresh Timer Control/Status Register (RTCSR)
The refresh timer control/status register (RTCSR) is a 16-bit readable/writable register that
specifies the refresh cycle and whether interrupts are to be generated.
RTSCR is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in
standby mode.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: —
—
—
—
—
—
—
—
Bit:
Initial value:
R/W:
7
CMF
0
R/W
6
CMIE
0
R/W
5
CKS2
0
R/W
4
CKS1
0
R/W
3
CKS0
0
R/W
2
OVF
0
R/W
1
OVIE
0
R/W
0
LMTS
0
R/W
Rev. 3.0, 04/02, page 354 of 1064