HD6417751 Datasheet, PDF (428/1105 Pages) Renesas Technology Corp – SuperH RISC engine

CKIO
Address
Tnop Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tce
c1
c2
c8
RD/
End of RAS down mode
D31–D0
(read)
d1
d2
d8
DACKn
(SA: IO ← memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.19(4) DRAM Burst Bus Cycle, RAS Down Mode Continuation
(EDO Mode, RCD = 0, AnW = 0)
Rev. 3.0, 04/02, page 388 of 1064