HD6417751 Datasheet, PDF (1059/1105 Pages) Renesas Technology Corp – SuperH RISC engine

TCLK
t_TCLKWH
t_TCLKWL
t_TCLKf
t_TCLKr
Figure 23.59 TCLK Input Timing
RTC internal clock
V_DD-RTC
V_DD-RTC min _tROSC
Oscillation settling time
Figure 23.60 RTC Oscillation Settling Time at Power-On
SCK, SCK2
t_SCKW
t_Scyc
t_SCKf
t_SCKr
Figure 23.61 SCK Input Clock Timing
SCK
TXD
RXD
t_Scyc
t_TXD t_TXD
t_RXS t_RXH
Figure 23.62 SCI I/O Synchronous Mode Clock Timing
Rev. 3.0, 04/02, page 1019 of 1064