HD6417751 Datasheet, PDF (1078/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Module Register
SCI SCSSR1
SCI SCRDR1
SCI SCSCMR1
SCI SCSPTR1
Area 7
Power-On
P4 Address Address*¹ Size Reset
H'FFE0 0010 H'1FE0 0010 8 H'84
H'FFE0 0014 H'1FE0 0014 8 H'00
H'FFE0 0018 H'1FE0 0018 8 H'00
H'FFE0 001C H'1FE0 001C 8 H'00*²
Manual
Reset
H'84
H'00
H'00
H'00*²
Synchro-
Stand- nization
Sleep by
Clock
Held H'84 Pclk
Held H'00 Pclk
Held H'00 Pclk
Held H'00*² Pclk
SCIF SCSMR2 H'FFE8 0000 H'1FE8 0000 16 H'0000
H'0000
Held Held Pclk
SCIF SCBRR2 H'FFE8 0004 H'1FE8 0004 8 H'FF
H'FF
Held Held Pclk
SCIF SCSCR2 H'FFE8 0008 H'1FE8 0008 16 H'0000
H'0000
Held Held Pclk
SCIF SCFTDR2 H'FFE8 000C H'1FE8 000C 8 Undefined Undefined Held Held Pclk
SCIF SCFSR2 H'FFE8 0010 H'1FE8 0010 16 H'0060
H'0060
Held Held Pclk
SCIF SCFRDR2 H'FFE8 0014 H'1FE8 0014 8 Undefined Undefined Held Held Pclk
SCIF SCFCR2 H'FFE8 0018 H'1FE8 0018 16 H'0000
H'0000
Held Held Pclk
SCIF SCFDR2 H'FFE8 001C H'1FE8 001C 16 H'0000
H'0000
Held Held Pclk
SCIF SCSPTR2 H'FFE8 0020 H'1FE8 0020 16 H'0000*²
H'0000*²
Held Held Pclk
SCIF SCLSR2 H'FFE8 0024 H'1FE8 0024 16 H'0000
H'0000
Held Held Pclk
H-UDI SDIR
H'FFF0 0000 H'1FF0 0000 16 H'FFFF*² Held
Held Held Pclk
H-UDI SDDR
H'FFF0 0008 H'1FF0 0008 32 Held
Held
Held Held Pclk
Hi-UDI SDINT
H'FFF0 0014 H'1FF0 0014 16 H'0000
Held
Held Held Pclk
Notes: *1 With control registers, the above addresses in the physical page number field can be
accessed by means of a TLB setting. When these addresses are set directly without
using the TLB, operations are limited.
*2 Includes undefined bits. See the descriptions of the individual modules.
*3 Use word-size access when writing. Perform the write with the upper byte set to H'5A or
H'A5, respectively. Byte- and longword-size writes cannot be used.
Use byte-size access when reading.
Rev. 3.0, 04/02, page 1038 of 1064